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never stop thinking. isoface tm ISO1H801G coreless transformer isolated digital output 8 channel 0.625a high-side switch datasheet , version 2.3, september 2009 power management & drives
ISO1H801G
type on-state resistance package ISO1H801G 200m ? ISO1H801G c (i.e c166) ad0 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p1.x vcc vcc parallel interface control unit ct control & protectio n unit cs wr d0 d1 d2 d3 d4 d5 d6 d7 dis vcc gndcc gndbb gnd out7 vbb vbb out1 out0 typical application reserved features ? interface 5v cmos operation compatible parallel interface direct control mode high common mode transient immunity short circuit protection maximum current internally limited overload protection overvoltage protection (including load dump) undervoltage shutdown with autorestart and hysteresis switching inductive loads common output disable pin thermal shutdown with restart thermal independence of separate channels esd protection loss of gndbb and loss of v bb protection reverse output voltage protection typical application isolated switch for indust rial applications (plc) all types of resistive, inductive and capacitive loads c compatible power switch for 24v dc applications driver for solenoid, relays and resistive loads description the ISO1H801G is a galvanically isolated 8 bit data interface in pg-dso-36 package that provides 8 fully protected high-side power switches that are able to handle currents up to 625 ma. an 8 bit parallel c compat ible interfac e allows to connect the ic directly to a c system. the input interface supports also a direct control mode and is designed to operate with 5v cmos compatible levels. the data transfer from input to output side is realized by the integrated coreless transformer technology.
isoface? ISO1H801G pin configuration and functionality datasheet 4 version 2.3, 2009-09-16 1 pin configuration and functionality 1.1 pin configuration pin symbol function 1 n.c. not connected 2 vcc positive 5v logic supply 3 dis cs wr vcc d1 1 dis cs wr 5 4 2 3 d3 d5 d2 d4 d0 6 7 8 9 10 d6 11 d7 12 reserved 13 gndcc 14 15 n.c. 16 17 18 36 32 33 35 34 31 30 29 28 27 26 25 24 23 22 21 20 19 out0 out2 out0 out1 out1 out3 out4 out3 out4 out2 out5 out5 out6 out6 gndbb out7 out7 n.c. n.c. n.c. n.c. vbb vbb tab tab figure 1 power so-36 (430mil) .
datasheet 5 version 2.3, 2009-09-16 isoface? ISO1H801G pin configuration and functionality 1.2 pin functionality vcc (positive 5v logic supply) the vcc supplies the input interface that is galvanically isolated from the output driver stage. the input interface can be supplied with 5v. dis (output disable) the high-side outputs out0...out7 can be immediately switched off by means of the low active pin ',6 that is an asynchronous signal. the input registers are also reset by the ',6 signal. the output remains switched off after low-high transition of dis signal, till new information is written into the input register. current sink to gndcc. &6 (chip select) the system microcontroller selects the ISO1H801G by means of the low active pin &6 to activate the parallel interface. by connecting the &6 pin and :5 pin to ground the parallel direct control is activated. current source to vcc. :5 (parallel write) in parallel mode data at the input pins (d0 ... d7) are latched by means of the rising edge of the low active signal :5 (write). current source to vcc. d0 ... d7 (data input bit0 ... bit7) the present data can be latched on the rising edge of the write signal :5 . d0 ... d7 control the corresponding output channels out0 ...out7. by connecting cs and :5 to ground, the signals at d0 ... d7 directly control the outputs. current sink to gndcc. gndcc (ground for vcc domain) this pin acts as the ground reference for the input interface that is supplied by vcc. gndbb (output driver ground domain) this pin acts as the ground reference for the output driver that is supplied by vbb. out0 ... out7 (high side output channel 0 ... 7) the output high side channels are internally connected to vbb and controlled by the corresponding data input pins d0 ... d7 in parallel mode. tab (vbb, positive supply for output driver) the heatslug is connected to the positive supply port of the output interface.
datasheet 6 version 2.3, 2009-09-16 isoface? ISO1H801G blockdiagram 2blockdiagram parallel input interface < d0 - d7 > d1 d2 d3 d4 d5 d6 d7 d0 wr cs overvoltage protection undervoltage shutdown with res tart voltage source common diagnostic output serial to parallel to logic channel 1 - 6 temperature sensor out0 overload protection current limitation limitation of unclamped inductive load logic charge pump level shifter rectifier high-side channel 0 temperature sensor out7 overload protection current limitation limitation of unclamped inductive load logic charge pump level shifter rectifier high-side channel 7 channel 1 ... 6 from temperatur e sensor channel 1 - 6 to logic channel 1 - 6 vbb logic undervoltage shutdown with restart vbb gndbb vcc gndcc galvanic isolation dis out1 out2 out3 out4 out5 out6 gate protection gate protection ISO1H801G direct mode contr ol reserved parallel to serial ct figure 2 blockdiagram
isoface? ISO1H801G functional description datasheet 7 version 2.3, 2009-09-16 3 functional description 3.1 introduction the isoface ISO1H801G includes 8 high-side power switches that are controlled by means of the integrated parallel interface. the interface is 8bit c compatible. furthermore a direct control mode can be selected that allows the direct control of the outputs out0...out7 by means of the inputs d0...d7 without any additional logic signal. the ic can replace 8 optocouplers and the 8 high-side switches in conventional i/o-applications as a galvanic isolation is implemented by means of the integrated coreless transformer technology. the c compatible interfac es allow a direct connection to the ports of a microcontroller without the need for other components. each of the 8 high-side power switches is protected against short to vbb, overload, overtemperature and against overvoltage by an active zener clamp. the diagnostic logic on the power chip recognizes the overtemperature information of each power transistor. 3.2 power supply the ic contains 2 galvanic isolated voltage domains that are independent from each other. the input interface is supplied at vcc and the output stage is supplied at vbb. the different voltage domains can be switched on at different time. the output stage is only enabled once the input stage enters a stable state. 3.3 output stage each channel contains a high-side vertical power fet that is protected by embedded protection functions. the continous current for each channel is 625ma (all channels on). 3.3.1 output stage control each output is independently controlled by an output latch and a common reset line via the pin dis wr cs cs vz vbb gndbb outx v on vbb figure 3 inductive and overvoltage output clamp (each channel) energy is stored in the load inductance during an inductive load switch-off. e l 12 e li l 2 u u = e l gndbb v bb outx e r l r l e load z l vbb e bb e as dx figure 4 inductive load switch-off energy dissipation (each channel) while demagnetizing the load inductance, the energy dissipation in the dmos is e as e bb e l e r ? v on cl i l t dt u = + = with an approximate solution for r l > 0 : e as i l l u 2r l u --------------- - v bb v on cl + 1 i l r l u v on cl ------------------------ - + ?1 ln u u = 3.3.3 power transistor overcurrent protection the outputs are provided with a current limitation that enters a repetitive switched mode after an initial peak current has been exceeded. the initial peak short circuit current limit is set to i l(scp) . during the repetitive mode short circuit current the limit is set to i l(scr) . if this operation leads to an overtemperature condition, a second protection level (t j > 135c) will change the
datasheet 8 version 2.3, 2009-09-16 isoface? ISO1H801G functional description output into a low duty cycle pwm (selective thermal shutdown with restart) to prevent critical chip temperatures. in vout t j t t t figure 5 overtemperatu re detection the following figures show the timing for a turn on into short circuit and a short circ uit in on-state. heating up of the chip may require several milliseconds, depending on external conditions. in vout i l t t t output short to gnd i l(scp) i l(scr) figure 6 turn on into short circuit, shut down by overtemperature, restart by cooling in vout i l t t t output short to gnd i l(scp) i l(scr) normal operation figure 7 short circuit in on-state, shut down down by overtemperature, restart by cooling 3.4 reserved
datasheet 9 version 2.3, 2009-09-16 isoface? ISO1H801G functional description 3.5 parallel interface the ISO1H801G contains a parallel interface that can be directly controlled by the microcontroller output ports. the parallel interface can also be switched over to a direct control that allows direct changes of the outputs out0 ... out7 by means of the corresponding inputs d0 ... d7 without additional logic signals. to activate the parallel direct control mode pin cs wr cs cs cs cs wr wr wr cs wr wr wr wr parallel interface ic1 output lines c (i.e c166) cs wr ad0 wr p0 p1 p2 p3 p4 p5 p6 p7 d0 d1 d2 d3 d4 d5 d6 d7 reserved vcc vcc vcc gndcc gnd figure 8 parallel bus configuration 3.5.3 direct control mode beside the use of the parallel c compatible interface a parallel direct control mode can be choosen. in this mode the output out0...out7 can be directly controlled via the inputs d0...d7 without the need for additional logic signals. to activate this mode pin cs wr parallel interface ic1 output lines controller p0 p1 p2 p3 p4 p5 p6 p7 d0 d1 d2 d3 d4 d5 d6 d7 vcc vcc vcc cs wr reserved gndcc gnd figure 9 parallel direct control
datasheet 10 version 2.3, 2009-09-16 isoface? ISO1H801G functional description 3.6 parallel interface timing cs wr data t whcs t wrpw d0 - d7 t ds t dh t cswr t csd out0 - out7 t on/off output figure 10 parallel input - output timing diagram 3.7 transmission failure detection there is a failure detection unit integrated to ensure also a stable functionality during the integrated coreless transformer transmission. this unit decides wether the transmitted data is valid or not. if four times serial data coming in from the internal registers is not accepted, the output stages are switched off until the next valid data is received.
isoface? ISO1H801G electrical characteristics datasheet 11 version 2.3, 2009-09-16 4 electrical characteristics note: all voltages at pins 2 to 14 are measured with respect to ground gndcc (pin 15). all voltages at pin 20 to pin 36 and tab are measured with respect to ground gndbb (pin 19). the voltage levels are valid if other ratings are not violated. the two voltage domains v cc and v bb are internally galvanic isolated. 4.1 absolute maximum ratings note: absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit. for the same reason make sure, that any capac itor that will be connected to pin 2 ( v cc) and tab (vbb) is discharged before assembling the application circuit. supply voltages higher than v bb(az) require an external current limit for the gndbb pin, e.g. with a 15 ? resistor in gndbb connection. operating at absolute maximum ratings can lead to a reduced lifetime. parameter at t j = -40 ... 135c, unless otherwise specified symbol limit values unit min. max. supply voltage input interface (vcc) v cc -0.5 6.5 v supply voltage output interface (vbb) v bb 1) defined by p tot -1 1) 45 continuous voltage at data inputs (d0 ... d7) v dx -0.5 6.5 continuous voltage at pin &6 v cs -0.5 6.5 continuous voltage at pin :5 v wr -0.5 6.5 continuous voltage at pin ',6 v dis -0.5 6.5 continuous voltage at reserved pin v reserved -0.5 6.5 load current (short-circuit current) i l ? ? ? ? ? ? ? ? ?
datasheet 12 version 2.3, 2009-09-16 isoface? ISO1H801G electrical characteristics 4.2 thermal characteristics parameter at t j = -25 ... 125c, v bb =15...30v, v cc =4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. thermal resistance junction - case r thjc ? ? ? ? ? ? at t j = -25 ... 125c, v bb =15...30v, v cc =4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. on-state resistance, i l = 0.5a t j = 25c t j = 125c r on ? ? ? ? ? ? ? ? ? ? ? at t j = -25 ... 125c, v bb =15...30v, v cc =4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. common mode transient immunity 1) ? ? ? ? ? ? ? ? ? ? ?
isoface? ISO1H801G electrical characteristics datasheet 13 version 2.3, 2009-09-16 4.5 output protection functions parameter 1) integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?out side? normal operating range. protection functions are not designed for continous repetitive operation. 1) at t j = -25 ... 125c, v bb =15...30v, v cc =4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. initial peak short circuit current limit, v bb = 30v, t m = 700s t j = -25c t j = 25c t j = 125c i l(scp) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
datasheet 14 version 2.3, 2009-09-16 isoface? ISO1H801G electrical characteristics 4.7 input interface parameter at t j = -25 ... 125c, v bb =15...30v, v cc =4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. input low state voltage (d0 ... d7, dis , cs , wr dis , cs , wr dis , cs , wr dis ) i idown 100 a input pull up current ( cs , wr output disable time (transition dis to logic low) 1)2) 1) the time includes the turn-on/off time of the high-side switch and the transmission time via the coreless transformer. 2) if pin dis is set to low the outputs are set to low; after dis set to high a new write cycle is nec essary to set the output again. normal operation turn-off time to 10% v out r l = 47 : t dis --- 85 170 s output disable time (transition dis to logic low) 3) the parameter is not subject to production test - verified by design/characterization 1)2)3) disturbed operation turn-off time to 10% v out r l = 47 : t dis --- --- 230 4.8 parallel interface input timing parameter at t j = -25 ... 125c, v bb =15...30v, v cc =4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. wr wr wr wr wr cs cs
isoface? ISO1H801G electrical characteristics datasheet 15 version 2.3, 2009-09-16 4.9 reverse voltage parameter at t j = -25 ... 125c, v bb =15...30v, v cc =4.5...5.5v, unless otherwise specified symbol limit values unit test condition min. typ. max. reverse voltage 1) defined by p tot 2) not subject to production test, specified by design 1)2) r gnd = 0 ? ? ? ? ? ? ? ? unless otherwise specified value unit conditions rated dielectric isolation voltage v iso 500 v ac 1 minute duration 1) the parameter is not subject to production test, verified by characterization; production test with 1100v, 100ms duration 1) minimum external air gap (clearance) 2.6 mm shortest distance through air. minimum external tracking (creepage) 2.6 mm shortest distance path along body. minimum internal gap 0.01 mm insulation distance through insulation note: for qualification report contact your local infineon technologies office!
datasheet 16 version 2.3, 2009-09-16 isoface? ISO1H801G electrical characteristics
datasheet 17 version 2.3, 2009-09-16 isoface? ISO1H801G electrical characteristics
datasheet 18 version 2.3, 2009-09-16 isoface? ISO1H801G package outlines 5 package outlines bottom view does not include plastic or metal protrusion of 0.15 max. per side 1 18 0.25 0.1 1.1 36 +0.13 0.25 36x 19 m (heatslug) 15.74 0.65 0.1 c ab 19 c 3.25 3.5 max. +0.1 0 0.1 0.1 36 2.8 b 11 0.15 1) 1.3 5 0.25 3 -0.02 +0.07 6.3 14.2 (mold) 0.3 b 0.15 0.25 heatslug 0.95 heatslug 0.1 5.9 3.2 (metal) 0.1 (metal) 13.7 (metal) 10 1 -0.2 index marking (mold) 15.9 1) 0.1 a 1 x 45 1) gps09181_1 pg-dso-36 (plastic dual small outline package) figure 11 pg-dso-36
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